One of the key devices of any computer system is a place to store data. Computer systems have many different places where data can be stored. One common place for storing massive amounts of data is a disc drive. The most basic parts of a disc drive are a disc that is rotated and on which data is stored, an actuator that moves a transducer to various locations over the disc, and electrical circuitry that is used to write data to and read data from the disc through the transducer. Data is stored on one or both surfaces of the disc. The disc drive also includes circuitry for encoding data written to the disc and for decoding data retrieved from the disc. A microprocessor controls most of the operations of a disc drive including passing information, such as instructions or data, read from the disc back to a requesting computer and taking information from the requesting computer for writing to the disc.
The disc drive communicates with other devices in a computer system such as the requesting computer over an interface. The performance of the computer system depends in part on the bandwidth of the interface. The bandwidth determines the speed with which information signals may be transmitted over the interface. The performance of the computer system improves with increases in the bandwidth of the interface which results in a faster transfer of information signals between the devices in the computer system.
A fibre channel is one example of an interface with a high bandwidth. The fibre channel is a standardized interface described in AMERICAN NATIONAL STANDARDS INSTITUTE, FIBRE CHANNEL--PHYSICAL AND SIGNALING INTERFACE (FC-PH) (Rev 4.3 1994). The fibre channel is a point-to-point physical interface, transmission protocol, and signaling protocol of a serial link for the support of higher level transmission protocols for controlling the communication of information including data and instructions. One of the higher level protocols is described in AMERICAN NATIONAL STANDARDS INSTITUTE, FIBRE CHANNEL--ARBITRATED LOOP (FC-AL-2) (Rev 6.3 1998).
Information signals, including data or instructions, are generated and manipulated in devices of the computer system as digital signals. The digital signals are manipulated and transferred inside the devices in bytes of 8 bits each. The bytes are encoded and expanded into transmission characters having 10 bits each, and put in serial form before being transmitted from a device over the fibre channel. The encoding is done according to an 8B/10B transmission code specified in FC-PH. The transmission characters are deserialized and decoded into bytes upon being received from the fibre channel in a succeeding device. Digital devices called 8B/10B encoders and decoders have been developed to carry out the encoding and decoding according to the 8B/10B transmission code.
The 8B/10B transmission code is a binary code comprising a series of "1's," also called high signals, and "0's," also called low signals. Each transmission character in the 8B/10B transmission code is comprised of either four 1's and six 0's, five 1's and five 0's, or six 1's and four 0's. The disparity of a transmission character is the difference between the number of 1's and the number of 0's. A transmission character with six 1's has a positive disparity, with five 1's has a neutral disparity, and with four 1's has a negative disparity. The 8B/10B encoders select the disparity of the transmission characters to maintain a balance between high and low signals transmitted over the fibre channel. For example, if a transmission character with a positive disparity is transmitted the 8B/10B encoder will keep track of the disparity and encode the following characters with either a neutral or a negative disparity. Similarly, if a transmission character with a negative disparity is transmitted the 8B/10B encoder will encode the following characters with either a neutral or a positive disparity.
Conventional8B/10B encoders are divided into two portions, a 5B/6B portion that encodes a 5 bit input into a 6 bit output, and a 3B/4B portion that encodes a 3 bit input into a 4 bit output. The encoding is completed in a single clock cycle. A disparity bit is passed from the 5B/6B portion to the 3B/4B portion to govern the disparity of the output bits based on the disparity of previously transmitted bits. Often two or more 8B/10B encoders are coupled in parallel to encode multiple bytes during a single clock cycle, and a disparity bit is passed or rippled through the encoders to govern the disparity of the output bits. The disparity bit may change depending on the disparity of the output bits in each portion of the 8B/10B encoders that the disparity bit passes through. The ripple of the disparity bit therefore absorbs a substantial amount of time, and each clock cycle must be long enough to allow the disparity bit to pass through each of the portions of the 8B/10B encoders before succeeding bytes are encoded in a subsequent clock cycle. The speed with which the 8B/10B encoders produces output bits to be transmitted has a substantial impact on the bandwidth of the fibre channel. There remains a need for 8B/10B encoder systems that encode bytes more rapidly to support higher bandwidths.
Summary of the Invention According to one embodiment of the present invention a number of input bits are received in a first encoder circuit and the input bits are encoded to generate encoded bits in the first encoder circuit. An input disparity bit is generated from the encoded bits, and the input bits and the input disparity bit are received in a second encoder circuit. The input bits are then encoded into a number of output bits based on the input disparity bit in the second encoder circuit. According to another embodiment of the present invention an encoder system includes a first encoder circuit having a number of inputs coupled to receive a number of input signals, to encode the input signals, and to generate a disparity signal at an output based on the encoded input signals. The encoder system also includes a second encoder circuit having a number of inputs coupled to receive the input signals and the disparity signal to encode the input signals into a number of output signals at a number of outputs based on the disparity signal.
Advantageously, the embodiments of the present invention generate a disparity signal for the input signals in the first encoder circuit before the input signals are encoded for transmission, and the disparity signal is provided to a second encoder circuit to encode the input signals with the desired disparity. The encoder system and the method eliminate the need for a disparity bit to migrate through two encoder circuits, and the encoding may be accomplished in a shorter time period. The encoder system and the method therefore encode input signals more rapidly than existing encoder systems.